The present invention relates to a design technique of a semiconductor integrated circuit device, and particularly to a technique useful for an optimization process of a layout process in a semiconductor integrated circuit device.
As a layout design technique of a semiconductor integrated circuit device, for example, a hierarchical design, a timing budget, and the like are widely known. The hierarchical design method is a technique by which a layout is designed by separating a plurality of low-order hierarchies (blocks) with a circuit scale operated by an automatic layout tool from a high-order hierarchy (top) that organizes these blocks.
In the hierarchical design method, the layouts of the top and the block are separately optimized as shown in, for example, FIG. 9. In every step, timing, congestion states, and the like are confirmed using all data, and an error in a timing estimation between the top and the block found at the time of the confirmation and a floorplan generated due to the error are amended.
As a layout design technique of a semiconductor integrated circuit device of this kind, there is known a technique in which when the entire chip is divided into a top and a plurality of blocks to perform arrangements of these blocks and wiring in these blocks, a semiconductor integrated circuit device is designed by using a block ILM which extracts data (logical data, physical data, and RC data) that belong to a block different from its own block and are associated with input and output of signals for its own block (for example, refer to Japanese Unexamined Patent Publication No. 2006-338090).